A) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a main circuit operating at a first voltage and a memory requiring an operation at a second voltage higher than the first voltage.
B) Description of the Related Art
An operation voltage of a semiconductor integrated circuit is lowering from 3 V to 2.5 V and to 1.25 V. A flash memory requires a high voltage of about 10 V. Because of its non-volatility performances, a flash memory is used in various logical integrated circuits. For example, the application range is broadening to logical integrated circuits mixedly mounting flash memories, such as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD). MOS transistors for controlling a memory requiring a high voltage such as a flash memory cell require a very high voltage. In order to realize a very high breakdown voltage of a MOS transistor, some design is necessary for determining an impurity concentration distribution of drain regions and wells, resulting in a considerable increase in the number of processes. In order not to increase the number of processes, it is desired to use general MOS transistors and operate the MOS transistors at a voltage higher than the drain breakdown voltage.
Techniques have been proposed which operate a MOS transistor at a voltage higher than the drain breakdown voltage. For example, two or more MOS transistors each formed in an independent well are connected in a cascade. As each MOS transistor is formed separately in an independent well, the device area becomes very large. If a plurality of MOS transistors are formed in one well and connected in a cascade, the breakdown voltage tends to be lowered. For these techniques, for example, refer to Japanese Patent Laid-open Publications No. 2000-323584 and HEI-11-133926.